1. Field of the System
The present system relates to field programmable gate array (FPGA) devices. More specifically, the system relates to a buffer module to increase the performance and utilization of an FPGA and a method of distributing buffer modules within an FPGA.
2. Background
FPGAs are known in the art. An FPGA comprises any number of logic modules, an interconnect routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. An FPGA is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into the array and the appropriate programmable elements are programmed to implement the necessary wiring connections that form the user circuit.
A field programmable gate array circuit can be programmed to implement virtually any set of digital functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user""s system, through input buffers and through the circuit, and finally back out the user""s system via output buffers. Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hystersis.
An FPGA core tile may be employed as a stand-alone FPGA, repeated in a rectangular array of core tiles, or included with other functions in a system-on-a-chip (SOC). The core FPGA tile may include an array of logic modules. An FPGA core tile may also include other components such as static random access memory (SRAM) modules. Horizontal and vertical routing channels provide interconnections between the various components within an FPGA core tile. Programmable connections are provided by programmable elements between the routing resources.
The programmable elements in an FPGA can be either one-time programmable or re-programmable. Re-programmable elements used in FPGA technologies include SRAM, EPROM, flash and other cell-controlled pass transistors or other re-programmable elements as is well known to those of ordinary skill in the art. One-time programmable elements used in FPGA technologies may comprise antifuse devices.
Antifuse devices are well known in the integrated circuit art. Antifuse devices comprise a pair of conductive electrodes separated by one or more layers of dielectric material. During programming, antifuses exhibit very high resistance between the two electrodes and may be considered to be small capacitators. For antifuses that are to be programmed, a programming process ruptures the dielectric material and creates a low-impedance connection between the two conductive electrodes.
In antifuse FPGAs, long tracks are problematic for both programming and normal operation. When programming, if there are too many antifuses on a track, the small amount of leakage current per antifuse can add up and cause the track not to remain at the proper voltage level when precharged or driven.
During normal operation, long routing tacks are problematic due to their large parasitic capacitances and resistances. This is exacerbated because unprogrammed antifuses act as small capacitors. The longer the routing track, the more antifuses the track will have.
Another issue when programming and operating an antifuse FPGA is high xe2x80x9cfanoutxe2x80x9d nets. This is a two-dimensional version of the long routing track problem. In a core tile, there are many logic modules, one of which may be a source module. The source module originates a signal that has to travel to any number of destination modules. The number of destination modules is known as the xe2x80x9cfanout.xe2x80x9d The paths between the source module and the destination modules is referred to as the net.
FIG. 1 is a simplified drawing showing the connectivity between a source module 2 and several destination modules 4 in an FPGA core tile. Source module 2 is located on a row adjacent to horizontal track 6. A row adjacent to single vertical track 8 is coupled to the output of source module 2 by means of an antifuse (not shown). Vertical track 8 is also coupled to a horizontal track in every channel by means of additional antifuses (not shown). This causes great capacitive loading and substantial series resistance resulting in a very slow propagation delay.
In prior-art FPGAs, the solution to the problem was buffering. In synthesis-based designs, if the auto-buffering tool was enabled, the design software would automatically insert buffers into the user netlist to comply with the maximum fanout rules and any timing data provided. In schematic-based designs, the user would have to enter the buffers into the schematics manually or let place-and-route software enter the buffers into the netlist for the user. The effect of adding the buffers in either the synthesis based designs or the schematic based designs is to break one long, complicated net driven by one driver, such as the one illustrated in FIG. 1, into multiple nets driven by multiple drivers.
However, there are problems with the approach set forth above. First, The logic modules in the FPGA core tile are used to buffer signals. Thus, the logic modules that are used to buffer signals are consequently unavailable to perform logic operations. In prior art antifuse FPGAs, approximately 12% of the logic modules are used as simple buffers. In some of the larger antifuse FPGAs the percentage of logic modules used as simple buffer modules could be as high as 25% or more. Also, logic modules are much more complicated and thus slower than simple buffers by a factor of approximately three. This significantly hinders performance when logic modules are used as buffers.
Hence there is a need for an FPGA buffering scheme that allows more of the logic modules in the FPGA to be used for logic functions rather than buffering, while maintaining a net size low enough to reduce the negative effects of long tracks.
The present system comprises a device and a method for increasing the performance and flexibility in a field programmable gate array. The device comprises a field programmable gate array having a plurality of interconnect conductors, a plurality of programmable elements, a plurality of input/output modules, and a plurality of logic clusters. The logic clusters each have a plurality of logic modules, at least one flip-flop, at least one buffer. Other modules, such as long distance transmitter and receiver modules may also be present.
The method of the present system comprises implementing buffers into an FPGA device comprised of a plurality of logic clusters. Each of said logic clusters has a buffer module. The method further comprises inputting a function netlist defining and optimizing a user circuit, which may or may not have gone through a round of auto buffering. Next, the cells comprising the user input are placed into the FPGA logic clusters. The function netlist is then analyzed to determine the placement of the buffer modules. At least one of the buffers is then selected for a post-placement function netlist. Next, at least one of the buffers is placed in the post-placement netlist. Next, a routing structure to interconnect the logic clusters to implement the user circuit is defined and a programming data file is generated. Finally, the programmable elements of one or more FPGA devices are programmed using the programming data.